Project Information d:\s3g15\lab5\serial\lab5.rpt MAX+plus II Compiler Report File Version 9.23 3/19/99 Compiled: 11/09/2000 16:27:02 Copyright (C) 1988-1999 Altera Corporation Any megafunction design, and related net list (encrypted or decrypted), support information, device programming or simulation file, and any other associated documentation or information provided by Altera or a partner under Altera's Megafunction Partnership Program may be used only to program PLD devices (but not masked PLD devices) from Altera. Any other use of such megafunction design, net list, support information, device programming or simulation file, or any other related documentation or information is prohibited for any other purpose, including, but not limited to modification, reverse engineering, de-compiling, or use with any other silicon devices, unless such use is explicitly licensed under a separate agreement with Altera or a megafunction partner. Title to the intellectual property, including patents, copyrights, trademarks, trade secrets, or maskworks, embodied in any such megafunction design, net list, support information, device programming or simulation file, or any other related documentation or information provided by Altera or a megafunction partner, remains with Altera, the megafunction partner, or their respective licensors. No other licenses, including any licenses needed under any third party's intellectual property, are provided herein. ***** Project compilation was successful ** DEVICE SUMMARY ** Chip/ Input Output Bidir Shareable POF Device Pins Pins Pins LCs Expanders % Utilized lab5 EPM7128SLC84-7 11 12 0 24 17 18 % User Pins: 11 12 0 Project Information d:\s3g15\lab5\serial\lab5.rpt ** PROJECT COMPILATION MESSAGES ** Warning: GLOBAL primitive on node 'Run' feeds logic -- non-global signal usage may result Project Information d:\s3g15\lab5\serial\lab5.rpt ** AUTO GLOBAL SIGNALS ** INFO: Signal 'Run' chosen for auto global Clear Project Information d:\s3g15\lab5\serial\lab5.rpt ** FILE HIERARCHY ** |74194:9| |74194:1| |74194:3| |7483:2| |74393:6| |74157:11| Device-Specific Information: d:\s3g15\lab5\serial\lab5.rpt lab5 ***** Logic for device 'lab5' compiled without errors. Device: EPM7128SLC84-7 Device Options: Turbo Bit = ON Security Bit = OFF Enable JTAG Support = ON User Code = ffff MultiVolt I/O = OFF R R E E V S S c C E E V l C R R C D o G I G R G G G V V C o c A B B N B A A N N u N N N Q E E I Q Q n k 0 3 1 D 2 3 2 T D n D D D 0 D D O 1 2 e -----------------------------------------------------------------_ / 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 | enable | 12 74 | C2 VCCIO | 13 73 | QA #TDI | 14 72 | GND RESERVED | 15 71 | #TDO RESERVED | 16 70 | QC RESERVED | 17 69 | QD RESERVED | 18 68 | RESERVED GND | 19 67 | C0 A1 | 20 66 | VCCIO B0 | 21 65 | Q3 RESERVED | 22 EPM7128SLC84-7 64 | C1 #TMS | 23 63 | QB RESERVED | 24 62 | #TCK RESERVED | 25 61 | RESERVED VCCIO | 26 60 | RESERVED RESERVED | 27 59 | GND RESERVED | 28 58 | RESERVED RESERVED | 29 57 | RESERVED RESERVED | 30 56 | RESERVED RESERVED | 31 55 | RESERVED GND | 32 54 | RESERVED |_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _| ------------------------------------------------------------------ R R R R R V R R R G V R R R G R R R R R V E E E E E C E E E N C E E E N E E E E E C S S S S S C S S S D C S S S D S S S S S C E E E E E I E E E I E E E E E E E E I R R R R R O R R R N R R R R R R R R O V V V V V V V V T V V V V V V V V E E E E E E E E E E E E E E E E D D D D D D D D D D D D D D D D N.C. = No Connect, This pin has no internal connection to the device. VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts). VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts). GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND. RESERVED = Unused I/O pin, which MUST be left unconnected. ^ = Dedicated configuration pin. + = Reserved configuration pin, which is tri-stated during user mode. * = Reserved configuration pin, which drives out in user mode. PDn = Power Down pin. @ = Special-purpose pin. # = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use. & = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions. Device-Specific Information: d:\s3g15\lab5\serial\lab5.rpt lab5 ** RESOURCE USAGE ** Shareable External Logic Array Block Logic Cells I/O Pins Expanders Interconnect A: LC1 - LC16 0/16( 0%) 8/ 8(100%) 0/16( 0%) 0/36( 0%) B: LC17 - LC32 0/16( 0%) 3/ 8( 37%) 0/16( 0%) 0/36( 0%) C: LC33 - LC48 0/16( 0%) 1/ 8( 12%) 0/16( 0%) 0/36( 0%) D: LC49 - LC64 0/16( 0%) 0/ 8( 0%) 0/16( 0%) 0/36( 0%) E: LC65 - LC80 0/16( 0%) 0/ 8( 0%) 0/16( 0%) 0/36( 0%) F: LC81 - LC96 0/16( 0%) 1/ 8( 12%) 0/16( 0%) 0/36( 0%) G: LC97 - LC112 8/16( 50%) 7/ 8( 87%) 9/16( 56%) 24/36( 66%) H: LC113 - LC128 16/16(100%) 6/ 8( 75%) 15/16( 93%) 22/36( 61%) Total dedicated input pins used: 1/4 ( 25%) Total I/O pins used: 26/64 ( 40%) Total logic cells used: 24/128 ( 18%) Total shareable expanders used: 17/128 ( 13%) Total Turbo logic cells used: 24/128 ( 18%) Total shareable expanders not available (n/a): 7/128 ( 5%) Average fan-in: 6.29 Total fan-in: 151 Total input pins required: 11 Total fast input logic cells required: 0 Total output pins required: 12 Total bidirectional pins required: 0 Total reserved pins required 4 Total logic cells required: 24 Total flipflops required: 17 Total product terms required: 95 Total logic cells lending parallel expanders: 0 Total shareable expanders in database: 13 Synthesized logic cells: 5/ 128 ( 3%) Device-Specific Information: d:\s3g15\lab5\serial\lab5.rpt lab5 ** INPUTS ** Shareable Expanders Fan-In Fan-Out Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name 10 (6) (A) INPUT 0 0 0 0 0 1 0 A0 20 (21) (B) INPUT 0 0 0 0 0 1 0 A1 4 (16) (A) INPUT 0 0 0 0 0 1 0 A2 5 (14) (A) INPUT 0 0 0 0 0 1 0 A3 21 (19) (B) INPUT 0 0 0 0 0 0 1 B0 8 (11) (A) INPUT 0 0 0 0 0 0 1 B1 6 (13) (A) INPUT 0 0 0 0 0 0 1 B2 9 (8) (A) INPUT 0 0 0 0 0 0 1 B3 11 (5) (A) INPUT 0 0 0 0 0 7 6 clock 12 (3) (A) INPUT 0 0 0 0 0 7 6 enable 1 - - INPUT G 0 0 0 0 0 4 4 Run Code: s = Synthesized pin or logic cell t = Turbo logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell G = Global Source. Fan-out destinations counted here do not include destinations that are driven using global routing resources. Refer to the Auto Global Signals, Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals Sections of this Report File for information on which signals' fan-outs are used as Clock, Clear, Preset, Output Enable, and synchronous Load signals. Device-Specific Information: d:\s3g15\lab5\serial\lab5.rpt lab5 ** OUTPUTS ** Shareable Expanders Fan-In Fan-Out Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name 67 104 G FF t 1 1 0 2 1 10 6 C0 (|74393:6|:1) 64 99 G FF t 1 1 0 2 2 2 1 C1 (|74393:6|:3) 74 117 H FF t 1 1 0 2 3 1 1 C2 (|74393:6|:5) 75 118 H OUTPUT t 0 0 0 0 3 0 0 Done 73 115 H FF t 1 1 0 2 2 1 0 QA (|74194:1|:41) 63 97 G FF t 1 1 0 2 2 1 0 QB (|74194:1|:40) 70 109 G FF t 1 1 0 2 2 1 0 QC (|74194:1|:39) 69 107 G FF t 1 1 0 2 2 3 6 QD (|74194:1|:38) 81 128 H FF t 0 0 0 2 5 4 6 Q0 (|74194:3|:38) 77 123 H FF t 2 0 1 2 7 3 6 Q1 (|74194:3|:39) 76 120 H FF t 0 0 0 2 2 2 5 Q2 (|74194:3|:40) 65 101 G FF t 5 0 0 2 12 1 2 Q3 (|74194:3|:41) Code: s = Synthesized pin or logic cell t = Turbo logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell Device-Specific Information: d:\s3g15\lab5\serial\lab5.rpt lab5 ** BURIED LOGIC ** Shareable Expanders Fan-In Fan-Out Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name - 119 H DFFE t 0 0 0 2 1 1 0 :8 - 127 H SOFT t 4 0 1 0 9 0 1 |7483:2|C4 (|7483:2|:83) (80) 126 H SOFT s t 1 0 1 0 7 1 0 |74194:3|~36~1 - 122 H SOFT s t 1 0 1 0 9 1 0 |74194:3|~36~2 - 114 H SOFT s t 1 0 1 0 9 1 0 |74194:3|~37~1 - 116 H SOFT s t 1 0 1 0 9 1 0 |74194:3|~37~2 - 121 H SOFT s t 1 0 1 0 9 1 0 |74194:3|~37~3 - 124 H DFFE t 2 2 0 4 0 2 6 |74194:9|QD (|74194:9|:38) (79) 125 H DFFE t 2 2 0 4 0 1 6 |74194:9|QC (|74194:9|:39) - 102 G DFFE t 2 2 0 4 0 1 6 |74194:9|QB (|74194:9|:40) - 103 G DFFE t 2 2 0 4 0 1 4 |74194:9|QA (|74194:9|:41) - 113 H TFFE t 1 1 0 2 4 3 1 |74393:6|Q1D (|74393:6|:9) Code: s = Synthesized pin or logic cell t = Turbo logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell Device-Specific Information: d:\s3g15\lab5\serial\lab5.rpt lab5 ** LOGIC CELL INTERCONNECTIONS ** Logic Array Block 'G': Logic cells placed in LAB 'G' +--------------- LC104 C0 | +------------- LC99 C1 | | +----------- LC97 QB | | | +--------- LC109 QC | | | | +------- LC107 QD | | | | | +----- LC101 Q3 | | | | | | +--- LC102 |74194:9|QB | | | | | | | +- LC103 |74194:9|QA | | | | | | | | | | | | | | | | Other LABs fed by signals | | | | | | | | that feed LAB 'G' LC | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'G': LC104-> * * * * * * - - | - - - - - - * * | <-- C0 LC97 -> - - - * - - - - | - - - - - - * - | <-- QB LC109-> - - - - * - - - | - - - - - - * - | <-- QC LC107-> - - - - - * - - | - - - - - - * * | <-- QD LC101-> - - - - - * - - | - - - - - - * * | <-- Q3 LC102-> - - - - - * - - | - - - - - - * * | <-- |74194:9|QB LC103-> - - - - - * - - | - - - - - - * * | <-- |74194:9|QA Pin 10 -> - - - - * - - - | - - - - - - * - | <-- A0 20 -> - - - * - - - - | - - - - - - * - | <-- A1 4 -> - - * - - - - - | - - - - - - * - | <-- A2 6 -> - - - - - - * - | - - - - - - * - | <-- B2 9 -> - - - - - - - * | - - - - - - * - | <-- B3 11 -> * * - - - * * * | - - - - - - * * | <-- clock 12 -> * * - - - * * * | - - - - - - * * | <-- enable 1 -> - - * * * - * * | - - - - - - * * | <-- Run LC115-> - - * - - - - - | - - - - - - * - | <-- QA LC128-> - - - - - * - - | - - - - - - * * | <-- Q0 LC123-> - - - - - * - - | - - - - - - * * | <-- Q1 LC120-> - - - - - * - - | - - - - - - * * | <-- Q2 LC119-> - - - - - * - - | - - - - - - * - | <-- :8 LC114-> - - - - - * - - | - - - - - - * - | <-- |74194:3|~37~1 LC116-> - - - - - * - - | - - - - - - * - | <-- |74194:3|~37~2 LC121-> - - - - - * - - | - - - - - - * - | <-- |74194:3|~37~3 LC113-> * * - - - - - - | - - - - - - * * | <-- |74393:6|Q1D * = The logic cell or pin is an input to the logic cell (or LAB) through the PIA. - = The logic cell or pin is not an input to the logic cell (or LAB). Device-Specific Information: d:\s3g15\lab5\serial\lab5.rpt lab5 ** LOGIC CELL INTERCONNECTIONS ** Logic Array Block 'H': Logic cells placed in LAB 'H' +------------------------------- LC117 C2 | +----------------------------- LC118 Done | | +--------------------------- LC115 QA | | | +------------------------- LC128 Q0 | | | | +----------------------- LC123 Q1 | | | | | +--------------------- LC120 Q2 | | | | | | +------------------- LC119 :8 | | | | | | | +----------------- LC127 |7483:2|C4 | | | | | | | | +--------------- LC126 |74194:3|~36~1 | | | | | | | | | +------------- LC122 |74194:3|~36~2 | | | | | | | | | | +----------- LC114 |74194:3|~37~1 | | | | | | | | | | | +--------- LC116 |74194:3|~37~2 | | | | | | | | | | | | +------- LC121 |74194:3|~37~3 | | | | | | | | | | | | | +----- LC124 |74194:9|QD | | | | | | | | | | | | | | +--- LC125 |74194:9|QC | | | | | | | | | | | | | | | +- LC113 |74393:6|Q1D | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Other LABs fed by signals | | | | | | | | | | | | | | | | that feed LAB 'H' LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H': LC117-> * * - - - - - - - - - - - - - * | - - - - - - - * | <-- C2 LC128-> - - * * * - - * * * * * * - - - | - - - - - - * * | <-- Q0 LC123-> - - - * * - - * * * * * * - - - | - - - - - - * * | <-- Q1 LC120-> - - - - * * - * - * * * * - - - | - - - - - - * * | <-- Q2 LC127-> - - - - - - * - - - - - - - - - | - - - - - - - * | <-- |7483:2|C4 LC126-> - - - - - * - - - - - - - - - - | - - - - - - - * | <-- |74194:3|~36~1 LC122-> - - - - - * - - - - - - - - - - | - - - - - - - * | <-- |74194:3|~36~2 LC124-> - - - * * - - * * * * * * - - - | - - - - - - - * | <-- |74194:9|QD LC125-> - - - - * - - * * * * * * - - - | - - - - - - - * | <-- |74194:9|QC LC113-> * - - - - - - - - - - - - - - * | - - - - - - * * | <-- |74393:6|Q1D Pin 5 -> - - * - - - - - - - - - - - - - | - - - - - - - * | <-- A3 21 -> - - - - - - - - - - - - - * - - | - - - - - - - * | <-- B0 8 -> - - - - - - - - - - - - - - * - | - - - - - - - * | <-- B1 11 -> * - - * * * * - - - - - - * * * | - - - - - - * * | <-- clock 12 -> * - - * * * * - - - - - - * * * | - - - - - - * * | <-- enable 1 -> - - * - - - - - - - - - - * * - | - - - - - - * * | <-- Run LC104-> * * * * * - - - * * * * * - - * | - - - - - - * * | <-- C0 LC99 -> * * - - - - - - - - - - - - - * | - - - - - - - * | <-- C1 LC107-> - - - * * - - * * * * * * - - - | - - - - - - * * | <-- QD LC101-> - - - - - - - * - * - - - - - - | - - - - - - * * | <-- Q3 LC102-> - - - - - - - * * * * * * - - - | - - - - - - * * | <-- |74194:9|QB LC103-> - - - - - - - * - - * * * - - - | - - - - - - * * | <-- |74194:9|QA * = The logic cell or pin is an input to the logic cell (or LAB) through the PIA. - = The logic cell or pin is not an input to the logic cell (or LAB). Device-Specific Information: d:\s3g15\lab5\serial\lab5.rpt lab5 ** EQUATIONS ** A0 : INPUT; A1 : INPUT; A2 : INPUT; A3 : INPUT; B0 : INPUT; B1 : INPUT; B2 : INPUT; B3 : INPUT; clock : INPUT; enable : INPUT; Run : INPUT; -- Node name is 'C0' = '|74393:6|Q1A' -- Equation name is 'C0', type is output C0 = TFFE( VCC, _EQ001, !_LC113, VCC, VCC); _EQ001 = _X001; _X001 = EXP( clock & enable); -- Node name is 'C1' = '|74393:6|Q1B' -- Equation name is 'C1', type is output C1 = TFFE( C0, _EQ002, !_LC113, VCC, VCC); _EQ002 = _X001; _X001 = EXP( clock & enable); -- Node name is 'C2' = '|74393:6|Q1C' -- Equation name is 'C2', type is output C2 = TFFE( _EQ003, _EQ004, !_LC113, VCC, VCC); _EQ003 = C0 & C1; _EQ004 = _X001; _X001 = EXP( clock & enable); -- Node name is 'Done' -- Equation name is 'Done', location is LC118, type is output. Done = LCELL( _EQ005 $ GND); _EQ005 = !C0 & !C1 & !C2; -- Node name is 'QA' = '|74194:1|QA' -- Equation name is 'QA', type is output QA = DFFE( _EQ006 $ GND, _EQ007, VCC, VCC, VCC); _EQ006 = Q0 & Run # A3 & !Run; _EQ007 = _X002; _X002 = EXP(!C0 & Run); -- Node name is 'QB' = '|74194:1|QB' -- Equation name is 'QB', type is output QB = DFFE( _EQ008 $ GND, _EQ009, VCC, VCC, VCC); _EQ008 = QA & Run # A2 & !Run; _EQ009 = _X002; _X002 = EXP(!C0 & Run); -- Node name is 'QC' = '|74194:1|QC' -- Equation name is 'QC', type is output QC = DFFE( _EQ010 $ GND, _EQ011, VCC, VCC, VCC); _EQ010 = QB & Run # A1 & !Run; _EQ011 = _X002; _X002 = EXP(!C0 & Run); -- Node name is 'QD' = '|74194:1|QD' -- Equation name is 'QD', type is output QD = DFFE( _EQ012 $ GND, _EQ013, VCC, VCC, VCC); _EQ012 = QC & Run # A0 & !Run; _EQ013 = _X002; _X002 = EXP(!C0 & Run); -- Node name is 'Q0' = '|74194:3|QD' -- Equation name is 'Q0', type is output Q0 = TFFE( _EQ014, _EQ015, GLOBAL( Run), VCC, VCC); _EQ014 = C0 & !Q0 & Q1 # !C0 & _LC124 & QD # C0 & Q0 & !Q1; _EQ015 = clock & enable; -- Node name is 'Q1' = '|74194:3|QC' -- Equation name is 'Q1', type is output Q1 = TFFE( _EQ016, _EQ017, GLOBAL( Run), VCC, VCC); _EQ016 = !C0 & _LC124 & !_LC125 & QD & Q0 # !C0 & _LC125 & QD & _X003 # C0 & !Q1 & Q2 # C0 & Q1 & !Q2; _X003 = EXP( _LC124 & Q0); _EQ017 = clock & enable; -- Node name is 'Q2' = '|74194:3|QB' -- Equation name is 'Q2', type is output Q2 = TFFE(!_EQ018, _EQ019, GLOBAL( Run), VCC, VCC); _EQ018 = !_LC122 & !_LC126; _EQ019 = clock & enable; -- Node name is 'Q3' = '|74194:3|QA' -- Equation name is 'Q3', type is output Q3 = TFFE(!_EQ020, _EQ021, GLOBAL( Run), VCC, VCC); _EQ020 = !_LC114 & !_LC116 & !_LC121 & _X004 & _X005 & _X006 & _X007 & _X008; _X004 = EXP(!C0 & !_LC102 & _LC103 & QD & !Q0 & !Q1); _X005 = EXP(!C0 & _LC102 & !_LC103 & QD & Q2); _X006 = EXP(!C0 & !_LC102 & _LC103 & QD & !Q2); _X007 = EXP( C0 & _LC119 & !Q3); _X008 = EXP( C0 & !_LC119 & Q3); _EQ021 = clock & enable; -- Node name is '|7483:2|:83' = '|7483:2|C4' -- Equation name is '_LC127', type is buried _LC127 = LCELL( _EQ022 $ GND); _EQ022 = _LC103 & _LC124 & QD & Q0 & _X009 & _X010 # _LC124 & QD & Q0 & Q3 & _X009 & _X010 # _LC125 & QD & Q1 & _X009 & _X011 # _LC102 & QD & Q2 & _X011 # _LC103 & QD & Q3; _X009 = EXP(!_LC102 & !Q2); _X010 = EXP(!_LC125 & !Q1); _X011 = EXP(!_LC103 & !Q3); -- Node name is '|74194:3|~36~1' -- Equation name is '_LC126', type is buried -- synthesized logic cell _LC126 = LCELL( _EQ023 $ GND); _EQ023 = !C0 & !_LC102 & _LC124 & _LC125 & QD & Q0 # !C0 & !_LC102 & _LC124 & QD & Q0 & Q1 # !C0 & !_LC102 & _LC125 & QD & Q1 # !C0 & _LC102 & !_LC125 & QD & !Q1 # !C0 & _LC102 & !_LC124 & QD & !Q1; -- Node name is '|74194:3|~36~2' -- Equation name is '_LC122', type is buried -- synthesized logic cell _LC122 = LCELL( _EQ024 $ GND); _EQ024 = !C0 & _LC102 & QD & !Q0 & !Q1 # !C0 & _LC102 & !_LC124 & !_LC125 & QD # !C0 & _LC102 & !_LC125 & QD & !Q0 # C0 & !Q2 & Q3 # C0 & Q2 & !Q3; -- Node name is '|74194:3|~37~1' -- Equation name is '_LC114', type is buried -- synthesized logic cell _LC114 = LCELL( _EQ025 $ GND); _EQ025 = !C0 & !_LC103 & _LC124 & QD & Q0 & Q1 & Q2 # !C0 & !_LC103 & _LC124 & _LC125 & QD & Q0 & Q2 # !C0 & _LC102 & !_LC103 & _LC124 & QD & Q0 & Q1 # !C0 & _LC102 & !_LC103 & _LC124 & _LC125 & QD & Q0 # !C0 & !_LC103 & _LC125 & QD & Q1 & Q2; -- Node name is '|74194:3|~37~2' -- Equation name is '_LC116', type is buried -- synthesized logic cell _LC116 = LCELL( _EQ026 $ GND); _EQ026 = !C0 & _LC102 & !_LC103 & _LC125 & QD & Q1 # !C0 & _LC103 & !_LC125 & QD & !Q1 & !Q2 # !C0 & _LC103 & !_LC124 & !_LC125 & QD & !Q2 # !C0 & _LC103 & !_LC125 & QD & !Q0 & !Q2 # !C0 & _LC103 & !_LC124 & QD & !Q1 & !Q2; -- Node name is '|74194:3|~37~3' -- Equation name is '_LC121', type is buried -- synthesized logic cell _LC121 = LCELL( _EQ027 $ GND); _EQ027 = !C0 & _LC103 & QD & !Q0 & !Q1 & !Q2 # !C0 & !_LC102 & _LC103 & !_LC125 & QD & !Q1 # !C0 & !_LC102 & _LC103 & !_LC124 & !_LC125 & QD # !C0 & !_LC102 & _LC103 & !_LC125 & QD & !Q0 # !C0 & !_LC102 & _LC103 & !_LC124 & QD & !Q1; -- Node name is '|74194:9|:41' = '|74194:9|QA' -- Equation name is '_LC103', type is buried _LC103 = DFFE( B3 $ GND, _EQ028, VCC, VCC, VCC); _EQ028 = _X012 & _X013; _X012 = EXP(!enable & Run); _X013 = EXP(!clock & Run); -- Node name is '|74194:9|:40' = '|74194:9|QB' -- Equation name is '_LC102', type is buried _LC102 = DFFE( B2 $ GND, _EQ029, VCC, VCC, VCC); _EQ029 = _X012 & _X013; _X012 = EXP(!enable & Run); _X013 = EXP(!clock & Run); -- Node name is '|74194:9|:39' = '|74194:9|QC' -- Equation name is '_LC125', type is buried _LC125 = DFFE( B1 $ GND, _EQ030, VCC, VCC, VCC); _EQ030 = _X012 & _X013; _X012 = EXP(!enable & Run); _X013 = EXP(!clock & Run); -- Node name is '|74194:9|:38' = '|74194:9|QD' -- Equation name is '_LC124', type is buried _LC124 = DFFE( B0 $ GND, _EQ031, VCC, VCC, VCC); _EQ031 = _X012 & _X013; _X012 = EXP(!enable & Run); _X013 = EXP(!clock & Run); -- Node name is '|74393:6|:9' = '|74393:6|Q1D' -- Equation name is '_LC113', type is buried _LC113 = TFFE( _EQ032, _EQ033, !_LC113, VCC, VCC); _EQ032 = C0 & C1 & C2; _EQ033 = _X001; _X001 = EXP( clock & enable); -- Node name is ':8' -- Equation name is '_LC119', type is buried _LC119 = DFFE( _LC127 $ GND, _EQ034, GLOBAL( Run), VCC, VCC); _EQ034 = clock & enable; -- Shareable expanders that are duplicated in multiple LABs: -- _X001 occurs in LABs G, H -- _X002 occurs in LABs G, H -- _X012 occurs in LABs G, H -- _X013 occurs in LABs G, H Project Information d:\s3g15\lab5\serial\lab5.rpt ** COMPILATION SETTINGS & TIMES ** Processing Menu Commands ------------------------ Design Doctor = off Logic Synthesis: Synthesis Type Used = Standard Default Synthesis Style = NORMAL Logic option settings in 'NORMAL' style for 'MAX7000S' family DECOMPOSE_GATES = on DUPLICATE_LOGIC_EXTRACTION = on MINIMIZATION = full MULTI_LEVEL_FACTORING = on NOT_GATE_PUSH_BACK = on PARALLEL_EXPANDERS = off REDUCE_LOGIC = on REFACTORIZATION = on REGISTER_OPTIMIZATION = on RESYNTHESIZE_NETWORK = on SLOW_SLEW_RATE = off SOFT_BUFFER_INSERTION = on SUBFACTOR_EXTRACTION = on TURBO_BIT = on XOR_SYNTHESIS = on IGNORE_SOFT_BUFFERS = off USE_LPM_FOR_AHDL_OPERATORS = off Other logic synthesis settings: Automatic Global Clock = on Automatic Global Clear = on Automatic Global Preset = on Automatic Global Output Enable = on Automatic Fast I/O = off Automatic Register Packing = off Automatic Open-Drain Pins = on Automatic Implement in EAB = off One-Hot State Machine Encoding = off Optimize = 5 Default Timing Specifications: None Cut All Bidir Feedback Timing Paths = on Cut All Clear & Preset Timing Paths = on Ignore Timing Assignments = on Functional SNF Extractor = off Linked SNF Extractor = off Timing SNF Extractor = on Optimize Timing SNF = off Generate AHDL TDO File = off Fitter Settings = NORMAL Smart Recompile = off Total Recompile = off Interfaces Menu Commands ------------------------ EDIF Netlist Writer = off Verilog Netlist Writer = off VHDL Netlist Writer = off Compilation Times ----------------- Compiler Netlist Extractor 00:00:00 Database Builder 00:00:00 Logic Synthesizer 00:00:00 Partitioner 00:00:00 Fitter 00:00:00 Timing SNF Extractor 00:00:00 Assembler 00:00:02 -------------------------- -------- Total Time 00:00:02 Memory Allocated ----------------- Peak memory allocated during compilation = 4,404K